14-Bit and 2GS/s Low Power Digitizing Boards for Physics Experiments

International audienceThe trend in data acquisition systems for modern physics experiments is to digitize analog signals closer and closer to the detector. The digitization systems have followed the progress of commercial analog to digital converters. The state of the art for these devices is currently 200 MSample/s for a 14-bit range. The new boards, described in this paper, have been designed to improve these performances by more than an order of magnitude. This board mainly includes 4 channels sampling analog data up to 2 GSamples/s with an analog bandwidth of 300 MHz, and digitizing it with a 14-bit dynamic range. It is based on the custom-designed MATACQ chip. The latter's innovative design permits reaching these performances with power consumption smaller than 1W, thus allowing a total consumption below 20W for the whole board. The board is triggerable either by internal or external signals and several boards are easily synchronizable. The board integrates USB, GPIB and VME interfaces that permit a readout speed of up to 500 events/s with the whole memory depth of the 4 channels read

Picosecond time measurement using ultra fast analog memories

International audienceThe currently existing electronics dedicated to precise time measurement is mainly based on the use of constant fraction discriminators (CFD) associated with Time to Digital Converters (TDC). The constant fraction technique minimizes the time walk effect (dependency of timing on the pulse amplitude). Several attempts have been made to integrate CFD in multi-channel ASICs. But the time resolution measured on the most advanced one is of the order of 30 ps rms. Two main techniques are used for the TDC architectures. The first one makes use of a voltage ramp started or stopped by the digital pulse. The obtained voltage is converted into digital data using an Analog to Digital Converter (ADC). The timing resolution of such a system is excellent (5 ps rms). But this technique is limited by its large dead time which can be unacceptable for the future high rate experiments. Another popular technique associates a coarse measurement performed by a digital counter with a fine measurement (interpolation) using Delay Line Loop. Such a system can integrate several (8-16) channels on an FPGA or an ASIC. The most advanced DLL-based TDC ASIC exhibits a timing resolution of 25 ps, but only after a careful calibration. It should be noticed that the overall timing resolution is given by the quadratic sum of the discriminator and of the TDC. In the meantime, alternative methods based on digital treatment of the analogue sampled then digitized detector signal have been developed. Such methods permit achieving a timing resolution far better than the sampling frequency. For example, 100ps rms resolution has been reported for a signal sampled at only 100MHz. Digitization systems have followed the progress of commercial ADCs, which currently offer a rate of 500 MHz over 12 bits. Their main drawbacks are the huge output data rate and power consumption. Their packaging, cooling, and tricky clock requirements also makes them very hard to implement. Conversely, high speed analog memories now offer sampling rates far above 1GHz at low cost and with low power consumption. The new USB-WaveCatcher board has been designed to provide high performances over a short time window. It houses on a small surface two 12-bit 500-MHz-bandwidth digitizers sampling between 400 MS/s and 3.2 GS/s. It is based on the patented SAM chip, an analog circular memory of 256 cells per channel. Its innovative matrix design permits reaching these performances, yet in a cheap pure CMOS 0.35µm technology, while consuming only 300 mW. Raw sampling precision is as good as 15ps rms. In an embodiment where the clock is directly sent to the SAM chip, thus limiting the usable sampling frequency to 3.2GHz, and after a calibration of the fixed pattern time distribution, a reproducible time precision of a few ps has been demonstrated. The board also offers various functionalities. Its input offset is tunable over a range of 2 V. It can be triggered either internally or externally and several boards can easily be synchronized. Trigger rates counters are implemented. Both channels can also be used for reflectometry thanks to their internal pulser. The precision obtained for cable length measurements is as good as 2mm. Charge measurement mode is also provided, through integrating on the fly over a programmable time window the signal coming for instance from photo-multipliers. Power consumption is only 2.5 W which permits powering with the sole USB. Signal connectors can be BNC, SMA or LEMO. The board houses a USB 12 Mbits/s interface permitting a dual-channel readout speed of 500 events/s. Faster readout modes are also available. In charge measurement mode, the sustained trigger rate can reach a few tens kHz. A 480Mbits/s version will soon be available. Various evolutions of the SAM chip are under study, targeting either higher precision time measurements or longer time window. The USB-WaveCatcher can thus replace oscilloscopes for a much lower cost in most high-precision short-window applications. Moreover, it opens new doors into the domain of very high precision time measurements

IDeF-X ASIC for Cd(Zn)Te spectro-imaging systems

Joint progresses in Cd(Zn)Te detectors, microelectronics and interconnection technologies open the way for a new generation of instruments for physics and astrophysics applications in the energy range from 1 to 1000 keV. Even working between -20 and 20 degrees Celsius, these instruments will offer high spatial resolution (pixel size ranging from 300 x 300 square micrometers to few square millimeters), high spectral response and high detection efficiency. To reach these goals, reliable, highly integrated, low noise and low power consumption electronics is mandatory. Our group is currently developing a new ASIC detector front-end named IDeF-X, for modular spectro-imaging system based on the use of Cd(Zn)Te detectors. We present here the first version of IDeF-X which consists in a set of ten low noise charge sensitive preamplifiers (CSA). It has been processed with the standard AMS 0.35 micrometer CMOS technology. The CSA are designed to be DC coupled to detectors having a low dark current at room temperature. The various preamps implemented are optimized for detector capacitances ranging from 0.5 up to 30 pF.Comment: 8 pages, 11 figures, IEEE NSS-MIC conference in Rome 2004, submitted to IEEE TNS, correction in unit of figure

A Low Power Multi-Channel Single Ramp ADC With Up to 3.2 GHz Virtual Clock

During the last decade, ADCs using single ramp architecture have been widely used in integrated circuits dedicated to nuclear science applications. These types of converters are actually very well suited for low power, multi-channel applications. Moreover their wide dynamic range and their very good differential non-linearity are perfectly matched to spectroscopy measurement. Unfortunately, their use is limited by their long conversion time, itself limited by their maximum clock frequency. A new architecture is described in this paper. It permits speeding up the conversion time of the traditional ramp ADC structures by a factor of 32 while keeping a low power consumption. Measurement results on a 4-channel, 12-bit prototype using a 3.2 GHz virtual clock are then presented in detail, showing excellent performances of linearity and noise

Using ultra fast analog memories for fast photo-detector readout

International audienceThe recent progresses in the field of photo-detection have pushed the performances of the detectors toward the picosecond scale. Currently existing electronics dedicated to precise charge and time measurement is mainly based on the use of high-end oscilloscopes. Numerous test benches are also based on both Charge-to-Amplitude Converters and Constant Fraction Discriminators (CFD) associated with Time to Digital Converters (TDC). The time resolution obtained with some commercial modules is very good (Time to Analog Converters ~ 5 ps rms after amplitude correction), but said modules house very few channels. Some TDC boards offer a higher number of channels, based on a coarse measurement performed by a digital counter associated with a fine measurement (interpolation) using Delay Line Loops, but their overall resolution is only of the order of 30 ps rms. Recently, alternative methods based on digital treatment of the analogue sampled then digitized detector signal have been developed. Such methods permit an easy calculation of the charge and amplitude, and achieve a timing resolution far better than the sampling frequency. Digitization systems have followed the progress of commercial ADCs, but the latter have prohibitory drawbacks like their huge output data rate and power consumption. Conversely, high speed analog memories now offer sampling rates far above 1GHz at low cost and with low power consumption. The new 16-channel WaveCatcher board has been designed to provide high performances over a short time window. It houses sixteen 12-bit 500-MHz-bandwidth digitizers sampling between 400 MS/s and 3.2 GS/s. It is based on the patented SAMLONG ASIC, a high-performance low-power analog circular memory designed in a cheap pure CMOS 0.35µm technology. The board offers a lot of functionalities like smart trigger configurations and embedded charge integration. It houses 480 Mbits/s USB and 1.5Gbits/s optical link interfaces. The board will soon been tested in different test benches dedicated to the characterization of fast MCP-PMTs or SiPMs, but a reproducible time precision better than 10 ps rms has already been demonstrated. The WaveCatcher board thus seems to be a powerful tool for photo-detector characterization and high-scale readout

SAM: A new GHz sampling ASIC for the H.E.S.S.-II front-end electronics

The H.E.S.S.-II front-end electronics, with its 20 GeV energy threshold, will require a much higher acquisition rate capability and a larger dynamic range than was relevant for H.E.S.S.-I. These constraints led to the development of a new ASIC, called SAM for Swift Analogue Memory, to replace the ARS used for H.E.S.S.-I. The SAM chip features 2 channels for the low and high gain outputs of a PMT, each channel having a depth of 256 analogue memory cells. The sampling frequency is adjustable from 0.7 up to 2 GS/s and the read-out time for one event is decreased from 275 down to 2.3 μs. The SAM input bandwidth and dynamic range are increased up to 300 MHz and more than 11 bits, respectively

The SAMPIC Waveform and Time to Digital Converter

Sce ElectroniqueInternational audienceSAMPIC is a Waveform and Time to DigitalConverter (WTDC) multichannel chip. Each of its 16 channelsassociates a DLL-based TDC providing a raw time with an ultrafastanalog memory allowing fine timing extraction as well asother parameters of the pulse. Each channel also integrates adiscriminator that can trigger itself independently or participateto a more complex trigger. After triggering, analog data isdigitized by an on-chip ADC and only that corresponding to aregion of interest is sent serially to the DAQ. The association ofthe raw and fine timings permits achieving timing resolutions of afew ps rms. The paper describes the detailed SAMPIC0architecture and reports its main measured performances

A transimpedance amplifier using a novel current mode feedback loop

We present a transimpedance amplifier stage based on a novel current mode feedback topology. This circuit employs NMOS and PMOS transistors exclusively and requires neither capacitor for stabilizing the transimpedance loop nor resistor for the transresistance feedback and transistor loading. This amplifier circuit is fully compatible with submicron digital CMOS processes. The active feedback network consists of two grounded-gate MOS devices which split the output current in both the feedback and output branches. The transresistance and the phase margin are adjustable through external DC signals. The measured rise time of the impulse response of the amplifier implemented in an industrial 0,7µm CMOS process is 18 ns for a transresistance of 180 k and 30 ns for a transresistance of 560 k. The measured Equivalent Noise Charge (ENC) is 800 rms e¯ for an input capacitance of 20 pF with the transresistance adjusted to 560 k

Development of a sampling ASIC for fast detector signals

International audienceIn the context of the Large Area Picosecond Photodetector (LAPPD) pro ject the motivation to measure time-of-flight at the picosecond reso- lution has pushed towards a faster signal rise-time (below 100 ps) and a higher bandwidth output (higher than 1 GHz) detector, thus, leading to a new signal development and integrity studies of Micro-Channel Plates (MCP) photo-detectors. Similarly, the signal path, is being simulated and characterized, from the anodes to the input of the readout electronics, to minimise losses. Furthermore, to acquire the detector fast pulses a new 10 Gs/s high input bandwidth, 130 nm CMOS sampling chip is being de- veloped